This invention relates to transistors, for example, transistors utilized in transmission gates.
Simple pass transistor networks are typically avoided in MOS technologies because of problems that arise due to degraded signal levels. For example, an N-channel MOS transistor will pass a logic zero without degradation, but will pass a logic one only within a threshold of the power supply rail. As a result, after several levels of pass transistors, a logic one may degrade to the point where it may be interpreted as a logic zero. Further, even if only one pass transistor is used, a static current will flow since an N-channel MOS transistor cannot pull a logic one up to the power supply rail. This static current is typically not tolerable in CMOS technology designs since both the N-channel and P-channel MOS transistors in a CMOS logic gate will be conducting current.
A transmission gate avoids the problem of signal degradation by employing both an N-channel and a P-channel MOS transistor to pass a signal whereby the first electrodes of the N-channel and P-channel MOS transistors are coupled to an input and the second electrodes of the N-channel and P-channel MOS transistors are coupled to the output of the transmission gate. Further, the gate electrode of the N-channel MOS transistor is coupled to a logic signal while the gate electrode of the P-channel MOS transistor is coupled to the inversion of the logic signal, as is understood. While the use of transmission gates facilitates the design of CMOS circuits, the testing of such circuits is extremely difficult. For instance, one way to test the transmission gate is to try and pass both a logic zero and a logic one through the transmission gate. While such a test will determine whether there is a failure that affects the entire transmission gate, it may not detect a failure in only one of the N-channel or P-channel MOS transistors. For example, assume that the transmission gate's P-channel MOS transistor has failed in such a way that it cannot be turned on. The transmission gate has therefore been reduced to the case of the simple pass transistor as aforementioned. Thus, the N-channel MOS transistor will pass logic zeros adequately. However, as aforedescribed, the N-channel MOS transistor will suffer timing and voltage degradations when trying to pass logic ones. It is important to note that the defective transmission gate, given sufficient time, will still function normally. Therefore, simple functional tests are unlikely to detect such failures.
One approach that can be used to detect a single transistor failure in transmission gates involves current monitoring so as to try and detect a static current. However, this approach is not practical for two reasons. First, current monitors are typically slower than modern test equipment and therefore testing will have to be slowed down. Second, the static current which results from a faulty transmission gate may not be significant compared to the load current typically drawn by the chip. Hence, the presence of the excess current would not even be detected.
Another approach which can be used to detect single transistor failures in transmission gates involves looking for an extra delay introduced by the failure. However, this approach is not practical for at least two reasons. First, delay tests are difficult to generate for large chips. Second, typically only the longest or sometimes nearly longest delay paths are tested. However, timing degradations caused by faulty transmission gates can be so severe that even normally fast paths become the longest delay path in the circuit. Thus, this normally short path would not be tested.
From the foregoing discussion, it is clear that transmission gates present a critical testing problem wherein under typical test conditions, the faulty chip will continue to function properly since simple functional tests will not detect single transistor failures within the transmission gate. Hence, there exists a need to provide a transmission gate that does not degrade performance when it fails.